Senior/RD Director (RTL) (07/631)

Jobinhalt

A global Tier-1 semiconductor group Taiwan branch RD team.

Responsibilities

Responsibility:

• Team buildup and management
• Determination of SoC Design-Specification and Development of Top level Architecture
• Architecture Design of BUS and Power,
• Logic Design and Verification
• TOP Level Sanity Check : Lint, CDC, Synthesis, EQ, ECO
• TOP level & Block level SDC generation and verification (PT constraint)
• TOP level & Block level UPF generation and verification (VC LP)
• Performance Profiling, Power Estimation
• Support of Physical Implementation
• Review and Check of Sub-Block Results according to Development Milestone
• Comprehensive project management
  

Industry: Semiconductor

Industry: IC Design

• SpringTW*This job is agented by Spring Professional Taiwan, The Adecco Group company.
  

Experience

• 15 years working experience with at least 5-year managerial expeirnce
• Familiar with RTL design(Verlilog, SystemVerilog)
• BUS - architecture and AXI/AXE protocol knowledge
• SoC design methodology knowledge
• Program language knowledge as like C, C++ etc.
  

Education

Engineering major with Master degree