Jobtyp: Full-time

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Jobinhalt

【工作內容】
  • Digital IP developing, digital circuit design & design verification
2.8-bit / 32-bit RISC/CISC CPU spec. define, chip base integration
  • Architecture design & integration (MCU/MPU)
  • Design flow setup and operation (Front-end: RTL coding, simulation, lint,… / Back-end: synthesis, DFT, STA,…)
  • Implementation of Chip DFT (Design for Test) solutions
【教育程度】碩士【擅長工具】
  • NC-Verilog or ModelSim
  • Synopsys DC/PT
  • SPYGLASS-LINT
  • Verilog
  • System-Verilog (for Design Verification)
【管理責任】否【工作經驗】無經驗【工作技能】Perl, Python, Synopsys, Verilog【其他】具有 MCU 產品設計經驗者或具有晶片量產經驗者尤佳
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Frist: 20-12-2024

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