CV Design Engineer

Job content

Position Summary: PDF is seeking an experienced Field Applications Engineer to join the Exensio® team, to serve serves as the primary contact for end-users of the software. Customers include both external and internal (consultant teams). End users of the Exensio® client software are typically Yield, Product, Test, Assembly, Process and Defect Engineers.

Responsibilities:

• Design, generate and verify specific Characterization Vehicle; test chip layouts to characterize clients’ manufacturing processes and quantify impact of design on product performance and yield. Focus on short flow (BEOL, FEOL) test chips.
• Use PDF proprietary automated layout tools including layout generators, routers and packers to create, place and route CV test chip structures.
• Generate all collateral needed for testing, inspection, analysis, and documentation of CV & reg; Test Chips.
• Participate with client in detailed review of test chip including post-OPC data review and pre mask-making reviews
• Work closely with PDF CV Analysis Methods to create an optimal design of experiments for CV® test chips.

Qualifications and Skills

· Master’s degree or higher in Engineering or related field

· Sound understanding of semiconductor manufacturing process and transistors.)

· Experience with semiconductor layout methods and layout tool suites (eg, Cadence, Mentor

• Working knowledge of DRC and LVS tools and deck creation and application
• Basic knowledge of Unix scripting languages (eg, perl, CSH, SH, Tcl, etc)
• Hands on experience with parametric test methods
• Self-motivated and highly professional including some experience with customer interactions
• Familiarity with interpreting and using Design Rule Manuals for deep sub-mic ron semiconductor processes (both foundry and IDM)
• Strong semiconductor Yield, Product, Process or Defect Engineering background.
• Excellent oral and written communications skills
• Highly professional, self-motivated and self-managed individual

Preferred Skills/Experience

• Hands on experience using Cadence Virtuoso and/or Cadence SKILL programming language
• Experience with Mentor Graphics Calibre DRC
• Responsible for any part of Design for Manufacturability including design modification, verification, algorithms or failure analysis
• Experience using circuit modeling software (HSPICE, Spectre, etc)
• Familiar with semiconductor reticle-making practices (mask data prep, dummy fill algorithms, basics of OPC , mask fracturing and biasing, etc)