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CPU Physical Design Lead
View: 171
Update day: 05-11-2024
Location: Banqiao District New Taipei City
Category: Design - Web Arts / Design Architecture / Interior Design IT - Software
Industry: Information Services Internet
Job type: Full-time
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Job content
Google welcomes people with disabilities.Minimum qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 10 years of experience with ASIC design implementation flows.
- Experience driving execution for physical design implementation with synthesis, Place and Route, and Static Timing Analysis tools.
- Experience in sign-off convergence including Static Timing Analysis, electrical checks, and physical verification.
- 5 years of industry experience on high-performance CPUs.
- Experience leading processor physical design teams.
- Experience delivering metric-driven Power Performance Area (PPA) goals.
- Knowledge of CPUs including critical iterations for timing and low-power microarchitecture and implementation techniques for CPUs.
- Proficiency in programming and scripting languages, such as Python, Tcl, and/or Perl.
In this role, you will be leading a physical design team for all market segments. You will collaborate with Physical Design, CAD, Architects,and Logic Designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure. You’ll also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
- Lead a physical design team.
- Drive design implementation for CPUs.
- Manage block and hierarchical physical implementation and QoR (power, timing, area).
- Collaborate with register-transfer level (RTL) design, cross-site Physical Design, and CAD teams on microarchitectural critical items for timing and power convergence.
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Deadline: 20-12-2024
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