ASIC RTL Engineer

Job content

Google welcomes people with disabilities.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 3 years of experience in RTL Design.
• Experience in ASIC or FPGA development with Verilog/SystemVerilog.
  
  

Preferred qualifications:

• Master’s degree in Electrical Engineering, Computer Science or a related field.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis and DFT.
• Experience with a scripting language like Perl or Python.
• Knowledge of high performance and low power design techniques, assertion-based formal verification, FPGA and emulation platforms and SoC architecture.
• Knowledge in one of the areas (e,g., memory compression, fabric, coherence, cache, DRAM, PHY).
  
  

About The Job

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user’s interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people’s lives better through technology.

Responsibilities

• Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
• Perform RTL coding, function/performance simulation debug, Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the block and SoC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .