ASIC Power Architect, Mitigation Lead, Silicon

Job content

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Minimum qualifications:

• Bachelor’s degree or equivalent practical experience.
• 10 years of experience in semiconductor design and development with a focus on low power design, implementation, and methodologies.
  
  

Preferred qualifications:

• Master’s degree or PhD in Electronics or Computer Engineering, or a related field.
• Experience in peak power management, in-rush current, Power Distribution Network (PDN) droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management, and thermal management.
• Experience with full product delivery cycle such as definition, architecture, design and implementation, testing, and productization.
• Understanding of techniques used to manage power delivery and thermal limits in modern SoCs and systems.
• Understanding of Power Management Integrated Circuits (PMICs), power delivery, board-level impedances, etc.
• Excellent communication, leadership, and organizational skills.
  
  

About The Job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Responsibilities

• Lead a small team of power engineers to drive peak power and voltage droop management and mitigation architectures and strategies for Google SoCs.
• Drive both pre-silicon design and post-silicon validation and tuning to optimize power and reduce design margins.
• Optimize user experience tradeoffs in the presence of peak power constraints.
• Collaborate with, influence, and provide leadership across a broad cross-functional audience spanning SoC architecture, various IPs, silicon engineering, system integration, power management architects, process/foundry technology, OS and Application Software teams.
• Represent this area to C-level executives across the organization.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .